Invention Grant
- Patent Title: Gate stack for heterostructure device
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Application No.: US16158560Application Date: 2018-10-12
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Publication No.: US11114539B2Publication Date: 2021-09-07
- Inventor: Jamal Ramdani
- Applicant: Power Integrations, Inc.
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Power Integrations, Inc.
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/51 ; H01L29/20 ; H01L29/205 ; H01L29/40 ; H01L29/423 ; H01L29/66 ; H01L21/28 ; H01L21/02

Abstract:
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. A sandwich gate dielectric layer structure is disposed on the second active layer. A passivation layer is disposed over the sandwich gate dielectric layer structure. A gate extends through the passivation layer to the sandwich gate dielectric layer structure. First and second ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
Public/Granted literature
- US20190115443A1 GATE STACK FOR HETEROSTRUCTURE DEVICE Public/Granted day:2019-04-18
Information query
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