Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16650928Application Date: 2018-09-11
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Publication No.: US11114565B2Publication Date: 2021-09-07
- Inventor: Hiroyuki Ota , Shinji Migita
- Applicant: National Institute of Advanced Industrial Science and Technology
- Applicant Address: JP Tokyo
- Assignee: National Institute of Advanced Industrial Science and Technology
- Current Assignee: National Institute of Advanced Industrial Science and Technology
- Current Assignee Address: JP Tokyo
- Agency: McCormick, Paulding & Huber PLLC
- Priority: JPJP2017-191369 20170929
- International Application: PCT/JP2018/033568 WO 20180911
- International Announcement: WO2019/065208 WO 20190404
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/40 ; H01L21/28 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L27/088 ; H01L27/1159 ; H01L29/06 ; H01L29/51 ; H01L29/66

Abstract:
Power consumption of a semiconductor device is reduced by sharpening the rise of a drain current when a gate voltage of a field effect transistor is less than a threshold voltage. As means therefor, in a fully-depleted MOSFET in which a thickness of a semiconductor layer serving as a channel region is 20 nm or less, a gate plug connected to a gate electrode is constituted of a first plug, a ferroelectric film, and a second plug sequentially stacked on the gate electrode. Here, an area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than an area where the gate electrode and a semiconductor layer serving as an active region overlap.
Public/Granted literature
- US20200243687A1 SEMICONDUCTOR DEVICE Public/Granted day:2020-07-30
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