Invention Grant
- Patent Title: Integrated circuit, test method for testing integrated circuit, and electronic device
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Application No.: US16816528Application Date: 2020-03-12
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Publication No.: US11115024B2Publication Date: 2021-09-07
- Inventor: Masato Oda , Shinichi Yasuda
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JPJP2019-166469 20190912
- Main IPC: H03K19/17728
- IPC: H03K19/17728 ; H03K19/1776 ; H03K17/80 ; H03K19/173 ; G01R31/317 ; G11C17/18 ; G11C17/16

Abstract:
An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.
Public/Granted literature
- US20210083672A1 INTEGRATED CIRCUIT, TEST METHOD FOR TESTING INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE Public/Granted day:2021-03-18
Information query
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