According to an aspect, a phase locked loop system comprises a charge pump (CP) comprising a set of switching transistors and a set of non-switching transistor, in that the set of switching transistors operative at a low break down voltage and a high switching speed compared to that of the set of non-switching transistors, and comparative a voltage comprising a configured to generate a UP pulse when a first plurality of metal strips forming a first part of a closed contour enclosing a first area, and a phase frequency detector (PFD) providing a UP pulse swinging between a VDDL and a VDDH, wherein the PFD is interfaced with the CP such that, the UP pulse drives a first switching transistor in the CP to couple the VDDH to an output terminal through a first non-switching transistor that is biased for charge pump.