Invention Grant
- Patent Title: Encoding circuit, decoding circuit, encoding method, decoding method, and transmitting device
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Application No.: US16996967Application Date: 2020-08-19
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Publication No.: US11115059B2Publication Date: 2021-09-07
- Inventor: Kazumasa Mikami , Junichi Sugiyama
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JPJP2019-164914 20190910
- Main IPC: H03M13/25
- IPC: H03M13/25 ; H03M13/11 ; H03M13/31 ; H03M13/33

Abstract:
An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.
Public/Granted literature
- US20210075444A1 ENCODING CIRCUIT, DECODING CIRCUIT, ENCODING METHOD, DECODING METHOD, AND TRANSMITTING DEVICE Public/Granted day:2021-03-11
Information query
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