The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC , a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR , and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR and an upper bit latch signal 15.