The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.