Invention Grant
- Patent Title: Wafer-level testing method and test structure thereof
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Application No.: US16249315Application Date: 2019-01-16
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Publication No.: US11121046B2Publication Date: 2021-09-14
- Inventor: Pei-Hsuan Lee , Yu-Hsuan Huang , Chia-Chia Kan
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G06T7/00 ; H01L21/67 ; G01R31/50

Abstract:
A method includes: coupling a first end of a first conductive trace to a free electron source; scanning exposed surfaces of the first and a second conductive traces with an electron beam, the first conductive trace and a second conductive trace being alternately arranged and spaced apart; obtaining an image of the first conductive trace and the second conductive trace while performing the scanning; and determining a routing characteristic of the first conductive trace and the second conductive trace based on the image.
Public/Granted literature
- US20200043815A1 WAFER-LEVEL TESTING METHOD AND TEST STRUCTURE THEREOF Public/Granted day:2020-02-06
Information query
IPC分类: