Invention Grant
- Patent Title: Gate-cut isolation structure and fabrication method
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Application No.: US16678320Application Date: 2019-11-08
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Publication No.: US11121132B2Publication Date: 2021-09-14
- Inventor: Haining Yang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: QUALCOMM Incorporated
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/70 ; H01L27/092 ; H01L21/8238 ; H01L29/78 ; H01L29/66 ; H01L21/762

Abstract:
Certain aspects of the present disclosure generally relate to a semiconductor device with a gate-cut isolation structure. An example method of fabricating semiconductor device generally includes forming a dielectric region between a first semiconductor region and a second semiconductor region. The method also includes forming a first gate region disposed above and spanning a width of the dielectric region between the first and second semiconductor regions, wherein the first gate region is also disposed above at least a portion of the first semiconductor region and above at least a portion of the second semiconductor region. The method further includes concurrently forming an SDB and a gate-cut isolation structure, wherein the SDB intersects the first and second semiconductor regions and wherein the gate-cut isolation structure electrically separates the first gate region into a first portion associated with the first semiconductor region and a second portion associated with the second semiconductor region.
Public/Granted literature
- US20210143152A1 GATE-CUT ISOLATION STRUCTURE AND FABRICATION METHOD Public/Granted day:2021-05-13
Information query
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