Invention Grant
- Patent Title: Method of making multiple nano layer transistors to enhance a multiple stack CFET performance
-
Application No.: US16592519Application Date: 2019-10-03
-
Publication No.: US11133310B2Publication Date: 2021-09-28
- Inventor: H. Jim Fulford , Mark I. Gardner
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/092 ; H01L21/822 ; H01L21/8238 ; H01L21/8258

Abstract:
A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in the first channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.
Public/Granted literature
- US20210104523A1 METHOD OF MAKING MULTIPLE NANO LAYER TRANSISTORS TO ENHANCE A MULTIPLE STACK CFET PERFORMANCE Public/Granted day:2021-04-08
Information query
IPC分类: