Method of making multiple nano layer transistors to enhance a multiple stack CFET performance
Abstract:
A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in the first channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.
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