Invention Grant
- Patent Title: Layout checking system and method
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Application No.: US16723965Application Date: 2019-12-20
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Publication No.: US11144704B2Publication Date: 2021-10-12
- Inventor: Yao-Jen Hsieh , Kai-Ming Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G06F30/398
- IPC: G06F30/398 ; G06F30/39 ; G06F30/392 ; H01L27/02 ; G06F119/18

Abstract:
A method includes operation below: extracting layout patterns that include interconnection layers between a first terminal and a second terminal coupled to the first terminal, in a layout design of a circuit; comparing a first portion of the layout patterns with a first coding portion that specifies a first layout constraint, in which the first portion of the layout patterns is extracted in a sequence starting from the first terminal or to the first terminal; comparing a second portion of the layout patterns with a second coding portion that specifies a second layout constraint, in which the second portion of the layout patterns is extracted in a sequence from the second terminal or to the second terminal; in response to comparisons, initiating fabrication of at least one element of the circuit according to the layout design.
Information query