Invention Grant

Memory device
Abstract:
According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.
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