A memory device that includes a memory array, a program circuit, a verify circuit and a controller is introduced. The program circuit is configured to apply a program pulse to at least one memory cell to set the at least one memory cell to a target state. The verify circuit is configured to perform a verify operation to determine whether the at least one memory cell reaches the predetermine threshold and to determine a number of failed memory cells among the at least one memory cell in response to determining that at least one of the at least one memory cell does not reach the target state. The controller is configured to adjust the program pulse according to the number of the failed memory cells to generate an adjusted program pulse that is applied to the failed memory cells to set the failed memory cells to the target state.