- Patent Title: Method for source/drain contact formation in semiconductor devices
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Application No.: US16688107Application Date: 2019-11-19
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Publication No.: US11145554B2Publication Date: 2021-10-12
- Inventor: Shao-Ming Koh , Chen-Ming Lee , I-Wen Wu , Fu-Kai Yang , Jia-Heng Wang , Mei-Yun Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L27/06 ; H01L21/02 ; H01L21/324 ; H01L21/768 ; H01L23/535 ; H01L27/092 ; H01L29/08 ; H01L29/16 ; H01L29/161 ; H01L29/167 ; H01L29/45 ; H01L29/165 ; H01L29/66 ; H01L21/306 ; H01L21/3065
Abstract:
A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.
Public/Granted literature
- US20200083118A1 Method for Source/Drain Contact Formation in Semiconductor Devices Public/Granted day:2020-03-12
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