- Patent Title: Calibration of residual errors using least-mean-squares (LMS) and stochastic-gradient methods for an analog-to-digital converter (ADC) with a pre-calibrated lookup table
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Application No.: US17140683Application Date: 2021-01-04
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Publication No.: US11146282B1Publication Date: 2021-10-12
- Inventor: Chi Fung Lok , Xiaoyong He , Zhi Jun Li
- Applicant: Caelus Technologies Limited
- Applicant Address: HK Hong Kong
- Assignee: Caelus Technologies Limited
- Current Assignee: Caelus Technologies Limited
- Current Assignee Address: HK Hong Kong
- Agency: gPatent LLC
- Agent Stuart T. Auvinen
- Main IPC: H03M1/10
- IPC: H03M1/10 ; H03M1/46 ; G06F7/544 ; H03M1/68

Abstract:
A first calibration measures capacitor array mis-match and updates a Look-Up Table (LUT) with calibrated weights that are copied to both a positive LUT and a negative LUT, and then adjusted for non-linearity errors by a second calibration using a Least Mean-Square (LMS) method. The binary code in the Successive-Approximation Register (SAR) is complemented to generate a complement code with a sign bit. When the sign bit is positive, entries for complement code bits=1 are read from the positive LUT and summed, a first offset added, and the sum normalized to get a corrected code. When the sign bit is negative, entries for complement code bits=0 are read from the negative LUT and summed, a second offset added, and the sum normalized to get the corrected code. A Multi-Variable Stochastic Gradient Descent method generates polynomial coefficients that further correct the corrected code.
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