Invention Grant
- Patent Title: Gate stacks for stack-fin channel I/O devices and nanowire channel core devices
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Application No.: US16201523Application Date: 2018-11-27
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Publication No.: US11152481B2Publication Date: 2021-10-19
- Inventor: Chao-Ching Cheng , Wei-Sheng Yun , I-Sheng Chen , Shao-Ming Yu , Tzu-Chiang Chen , Chih Chieh Yeh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/786 ; H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L27/092 ; H01L29/10 ; H01L27/06 ; H01L21/8238 ; H01L29/775 ; H01L29/40 ; H01L29/165

Abstract:
A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.
Public/Granted literature
- US20190109204A1 Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices Public/Granted day:2019-04-11
Information query
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