Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US16920936Application Date: 2020-07-06
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Publication No.: US11158654B2Publication Date: 2021-10-26
- Inventor: Shunpei Yamazaki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi
- Agency: Robinson IP Law Office, P.C.
- Agent Eric J. Robinson
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/786 ; H01L29/66

Abstract:
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
Public/Granted literature
- US20200335525A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-10-22
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