Invention Grant
- Patent Title: Double patterning method
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Application No.: US16837252Application Date: 2020-04-01
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Publication No.: US11177138B2Publication Date: 2021-11-16
- Inventor: Chia-Ying Lee , Jyu-Horng Shieh
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/768 ; H01L21/033 ; H01L21/027

Abstract:
The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.
Public/Granted literature
- US20200234972A1 DOUBLE PATTERNING METHOD Public/Granted day:2020-07-23
Information query
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