- Patent Title: Semiconductor device with top die positioned to reduce die cracking
-
Application No.: US16814761Application Date: 2020-03-10
-
Publication No.: US11177241B2Publication Date: 2021-11-16
- Inventor: Junrong Yan , Jianming Zhang , Min Zhao , Kailei Zhang , Chee Keong Chin , Kim Lee Bock
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Priority: CN201910469575.0 20190531
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00
Abstract:
A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
Public/Granted literature
- US20200381401A1 SEMICONDUCTOR DEVICE WITH TOP DIE POSITIONED TO REDUCE DIE CRACKING Public/Granted day:2020-12-03
Information query
IPC分类:
