Invention Grant
- Patent Title: Stacked vertical field effect transistor with self-aligned junctions
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Application No.: US16582790Application Date: 2019-09-25
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Publication No.: US11177369B2Publication Date: 2021-11-16
- Inventor: Lan Yu , Xin Miao , Chen Zhang , Heng Wu , Kangguo Cheng
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael A. Petrocelli
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L29/66 ; H01L29/423 ; H01L21/02 ; H01L29/78 ; H01L29/06

Abstract:
A method of forming a semiconductor device and resulting structure in which a trench is formed extending through a plurality of layers on a semiconductor substrate. The plurality of layers includes a sequence of dielectric materials. A first portion of the plurality of layers corresponds to a bottom vertical field effect transistor (VFET) and a second portion of the plurality of layers corresponds to a top VFET. A sacrificial layer separates the bottom VFET from the top VFET. A fin is formed within the trench by epitaxially growing a semiconductor material. A hard mask is formed above a central portion of the plurality of layers. Portions of the plurality of layers not covered by the hard mask are removed. The first portion of the plurality of layers is covered to remove the sacrificial layer. The recess resulting from the removal of the sacrificial layer is filled with an oxide material.
Public/Granted literature
- US20210091207A1 STACKED VERTICAL FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED JUNCTIONS Public/Granted day:2021-03-25
Information query
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