Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.