Invention Grant
- Patent Title: VLAN-aware clock hierarchy
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Application No.: US16752280Application Date: 2020-01-24
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Publication No.: US11184097B2Publication Date: 2021-11-23
- Inventor: Harold Fong , Petr Budnik , Jeff Jing Yuen Chan
- Applicant: Arista Networks, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Arista Networks, Inc.
- Current Assignee: Arista Networks, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Fountainhead Law Group P.C.
- Main IPC: H04J3/06
- IPC: H04J3/06 ; H04L12/931 ; H04L12/46 ; H04L7/00

Abstract:
Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master/slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port.
Public/Granted literature
- US20210050927A1 VLAN-Aware Clock Hierarchy Public/Granted day:2021-02-18
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