A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.