Invention Grant
- Patent Title: Process to yield ultra-large integrated circuits and associated integrated circuits
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Application No.: US16789210Application Date: 2020-02-12
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Publication No.: US11189558B2Publication Date: 2021-11-30
- Inventor: David Madajian
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/532

Abstract:
An integrated circuit includes a first conductive layer and a first insulation layer formed on the first conductive layer. The integrated circuit also includes a second insulation layer formed on the first insulation layer and a second conductive layer formed on the second insulation layer. The first insulation layer may include a first defect, and the second insulation layer may include a second defect. The integrated circuit may also include a third insulation layer formed on the second conductive layer, a fourth insulation layer formed on the third insulation layer, and a third conductive layer formed on the fourth insulation layer. The third insulation layer may include a third defect, and the fourth insulation layer may include a fourth defect.
Public/Granted literature
- US20210249346A1 PROCESS TO YIELD ULTRA-LARGE INTEGRATED CIRCUITS AND ASSOCIATED INTEGRATED CIRCUITS Public/Granted day:2021-08-12
Information query
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