Invention Grant
- Patent Title: Platform interface layer and protocol for accelerators
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Application No.: US15836856Application Date: 2017-12-09
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Publication No.: US11194753B2Publication Date: 2021-12-07
- Inventor: Pratik M. Marolia , Stephen S. Chang , Nagabhushan Chitlur , Michael C. Adler
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F13/42 ; G06N3/08 ; G06F9/455

Abstract:
There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.
Public/Granted literature
- US20190042518A1 PLATFORM INTERFACE LAYER AND PROTOCOL FOR ACCELERATORS Public/Granted day:2019-02-07
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