Platform interface layer and protocol for accelerators
Abstract:
There is disclosed in one example an accelerator apparatus, including: a programmable region capable of being programmed to provide an accelerator function unit (AFU); and a platform interface layer (PIL) to communicatively couple to the AFU via an intra-accelerator protocol, and to provide multiplexed communication with a processor via a plurality of platform interconnect interfaces, wherein the PIL is to provide abstracted communication services for the AFU to communicate with the processor.
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