A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.