Invention Grant
- Patent Title: Back-end-of-line compatible processing for forming an array of pillars
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Application No.: US16735020Application Date: 2020-01-06
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Publication No.: US11195995B2Publication Date: 2021-12-07
- Inventor: Chi-Chun Liu , Yann Mignot , Ekmini Anuja De Silva , Nelson Felix , John Christopher Arnold
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Abdy Raissinia
- Main IPC: H01L43/12
- IPC: H01L43/12 ; H01L43/02 ; H01L27/22

Abstract:
A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.
Public/Granted literature
- US20210210679A1 BACK-END-OF-LINE COMPATIBLE PROCESSING FOR FORMING AN ARRAY OF PILLARS Public/Granted day:2021-07-08
Information query
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