An arithmetic processing apparatus includes: a memory; and a processor coupled to the memory, wherein the processor: detects whether intervals of a plurality of addresses to be accessed by a memory access instruction that performs memory access to the plurality of addresses by a single instruction are all the same; decodes the memory access instruction as the single instruction when detecting that the intervals are all the same; decodes the memory access instruction as a plurality of instructions when detecting that the intervals are not all the same; and performs the memory access in accordance with the single instruction or the plurality of instructions.