Invention Grant
- Patent Title: Processor with a program counter increment based on decoding of predecode bits
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Application No.: US15612247Application Date: 2017-06-02
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Publication No.: US11200059B2Publication Date: 2021-12-14
- Inventor: Hirokazu Hanaki , Satoshi Takashima
- Applicant: SONY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SONY CORPORATION
- Current Assignee: SONY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Chip Law Group
- Priority: JPJP2010-203910 20100913
- Main IPC: G06F9/32
- IPC: G06F9/32 ; G06F9/30 ; G06F9/38
Abstract:
A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.
Public/Granted literature
- US20170277540A1 Processor with a Program Counter Increment Based on Decoding of Predecode Bits Public/Granted day:2017-09-28
Information query
