Invention Grant
- Patent Title: Three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns and method of manufacturing the same
-
Application No.: US16582240Application Date: 2019-09-25
-
Publication No.: US11201166B2Publication Date: 2021-12-14
- Inventor: Eun Yeoung Choi , Hyung Joon Kim , Su Hyeong Lee , Yong Seok Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2019-0064724 20190531
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11556

Abstract:
A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.
Public/Granted literature
- US20200381446A1 THREE DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2020-12-03
Information query
IPC分类: