Invention Grant
- Patent Title: Cascode amplifier circuit
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Application No.: US16784494Application Date: 2020-02-07
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Publication No.: US11201594B2Publication Date: 2021-12-14
- Inventor: Nobuyasu Beppu
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Kyoto
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Pearne & Gordon LLP
- Priority: JPJP2017-156173 20170810
- Main IPC: H03F1/22
- IPC: H03F1/22 ; H03F1/02 ; H03F1/34 ; H03F3/195

Abstract:
An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.
Public/Granted literature
- US20200177135A1 CASCODE AMPLIFIER CIRCUIT Public/Granted day:2020-06-04
Information query
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