Invention Grant
- Patent Title: Wear leveling in solid state devices
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Application No.: US16827605Application Date: 2020-03-23
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Publication No.: US11204697B2Publication Date: 2021-12-21
- Inventor: Kanishk Rastogi , Sanoj Kizhakkekara Unnikrishnan , Anand Mitra
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02

Abstract:
Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100-p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.
Public/Granted literature
- US20200225850A1 Wear Leveling in Solid State Devices Public/Granted day:2020-07-16
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