- Patent Title: Retention-aware data tiering algorithm for hybrid storage arrays
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Application No.: US16293393Application Date: 2019-03-05
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Publication No.: US11204705B2Publication Date: 2021-12-21
- Inventor: Chao Sun , Pi-Feng Chiu , Dejan Vucinic
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patent Law Works LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/02 ; G06N20/00

Abstract:
A memory array controller includes memory media scanning logic to sample a bit error rate of memory blocks of a first memory device. A data management logic may then move data from the first memory device to a second memory device if the bit error rate matches a threshold level. The threshold level is derived from a configurable data retention time parameter for the first memory device. The configurable data retention time parameter may be received from a user or determined utilizing various known machine learning techniques.
Public/Granted literature
- US20200285391A1 RETENTION-AWARE DATA TIERING ALGORITHM FOR HYBRID STORAGE ARRAYS Public/Granted day:2020-09-10
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