A processing device in a memory system receives, from a host system, a request for a debug slave address associated with a system management bus port of a memory sub-system and sends a response comprising the debug slave address to the host system. The processing device receives, from the host system, a request to enable the system management bus port to receive a request for debug information directed to the debug slave address, receives, from the host system, the request for debug information directed to the debug slave address, and sends the debug information to the host system over a system management bus coupled to the system management bus port of the memory sub-system.