Invention Grant
- Patent Title: Ferroelectric memory and logic cell and operation method
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Application No.: US16782441Application Date: 2020-02-05
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Publication No.: US11205467B2Publication Date: 2021-12-21
- Inventor: Stefan Slesazeck , Milan Pesic
- Applicant: NaMLab gGmbH
- Applicant Address: DE Dresden
- Assignee: NaMLab gGmbH
- Current Assignee: NaMLab gGmbH
- Current Assignee Address: DE Dresden
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C11/22
- IPC: G11C11/22 ; G06N3/063

Abstract:
One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.
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