A matrix converter control device includes a plurality of delay circuits which correspond to logic change timings of a plurality of input pulse width modulation (PWM) signals for controlling ON and OFF states of a plurality of switching elements included in a matrix converter. Specifically, the plurality of delay circuits are a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, and a fifth delay circuit. Each of the plurality of delay circuits delays an input PWM signal by an amount of delay set for the delay circuit at a logic change timing corresponding to the delay circuit.