Invention Grant
- Patent Title: Process for integrated circuit fabrication using a buffer layer as a stop for chemical mechanical polishing of a coupled dielectric oxide layer
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Application No.: US17096434Application Date: 2020-11-12
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Publication No.: US11211254B2Publication Date: 2021-12-28
- Inventor: Yuzhan Wang , Pradeep Basavanahalli Kumarswamy , Hong Kia Koh , Alberto Leotti , Patrice Ramonda
- Applicant: STMicroelectronics Pte Ltd
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics Pte Ltd
- Current Assignee: STMicroelectronics Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: Crowe & Dunlevy
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/762 ; H01L21/768

Abstract:
A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.
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