Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US16521596Application Date: 2019-07-25
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Publication No.: US11211350B2Publication Date: 2021-12-28
- Inventor: Hung-Hsin Hsu , Shang-Yu Chang Chien , Nan-Chun Lin
- Applicant: Powertech Technology Inc.
- Applicant Address: TW Hsinchu County
- Assignee: Powertech Technology Inc.
- Current Assignee: Powertech Technology Inc.
- Current Assignee Address: TW Hsinchu County
- Agency: JCIPRNET
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L23/29 ; H01L23/31 ; H01L21/768 ; H01L23/522 ; H01L23/538 ; H01L25/065

Abstract:
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.
Public/Granted literature
- US20200273829A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2020-08-27
Information query
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