Invention Grant
- Patent Title: Semiconductor memory structure having drain stressor, source stressor and buried gate and method of manufacturing the same
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Application No.: US16520569Application Date: 2019-07-24
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Publication No.: US11211491B2Publication Date: 2021-12-28
- Inventor: Cheng-Hsiang Fan
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/762 ; H01L21/02 ; G11C5/06

Abstract:
The present disclosure provides a semiconductor memory structure and a method for preparing the semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.
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Information query
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