Invention Grant
- Patent Title: Pin count socket having reduced pin count and pattern transformation
-
Application No.: US16888069Application Date: 2020-05-29
-
Publication No.: US11212932B2Publication Date: 2021-12-28
- Inventor: Srikant Nekkanty , Zhichao Zhang , Kemal Aygun
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01R12/00
- IPC: H01R12/00 ; H05K7/10 ; H05K1/11 ; H05K7/14 ; H05K1/02

Abstract:
An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.
Public/Granted literature
- US20200296852A1 PIN COUNT SOCKET HAVING REDUCED PIN COUNT AND PATTERN TRANSFORMATION Public/Granted day:2020-09-17
Information query