Invention Grant
- Patent Title: Marker layout method for optimizing overlay alignment in semiconductor device
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Application No.: US16894700Application Date: 2020-06-05
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Publication No.: US11215932B2Publication Date: 2022-01-04
- Inventor: Sung Jae Kim , Song Yi Jeon , Chang Ouk Kim , Ki Bum Lee
- Applicant: SK hynix Inc. , UIF (University Industry Foundation), Yonsei University
- Applicant Address: KR Icheon; KR Seoul
- Assignee: SK hynix Inc.,UIF (University Industry Foundation), Yonsei University
- Current Assignee: SK hynix Inc.,UIF (University Industry Foundation), Yonsei University
- Current Assignee Address: KR Icheon; KR Seoul
- Priority: KR10-2019-0108778 20190903
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.
Public/Granted literature
- US20210063895A1 MARKER LAYOUT METHOD FOR OPTIMIZING OVERLAY ALIGNMENT IN SEMICONDUCTOR DEVICE Public/Granted day:2021-03-04
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