A solid state memory system includes: an interface circuit; a device processor configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled to the device processor, configured by the device processor, the power manager unit configured to adjust voltages for read, write, erase, and monitoring a voltage feedback in order to verify the dynamic power limit command is not exceeded; and a data error detection-and-correction unit, coupled to the power manager unit, configured to pause correction of error data, select a low power error correction code unit, enable a reduced ECC array, switch from error detection-and-correction to error detection, or a combination thereof in response to the dynamic power limit command.