Invention Grant
- Patent Title: Weight matrix circuit and weight matrix input circuit
-
Application No.: US16450968Application Date: 2019-06-24
-
Publication No.: US11216728B2Publication Date: 2022-01-04
- Inventor: Jae-Joon Kim , Taesu Kim , Hyungjun Kim
- Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Applicant Address: KR Pohang-si
- Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
- Current Assignee Address: KR Pohang-si
- Agency: Morgan, Lewis & Bockius LLP
- Priority: KR10-2018-0072808 20180625
- Main IPC: G06N3/08
- IPC: G06N3/08 ; G11C13/00 ; G11C11/16 ; G11C11/22

Abstract:
Provided are a weight matrix circuit and a weight matrix input circuit. The weight matrix circuit includes a memory array including n input lines, m output lines, and n×m resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic, an input circuit connected to each of the input lines, and an output circuit connected to each of the output lines. The input circuit is connected to the resistive memory devices such that the weight matrix circuit has a linear current-voltage characteristic.
Public/Granted literature
- US20190392316A1 WEIGHT MATRIX CIRCUIT AND WEIGHT MATRIX INPUT CIRCUIT Public/Granted day:2019-12-26
Information query