Invention Grant
- Patent Title: Semiconductor arrangement and method of manufacture
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Application No.: US16687999Application Date: 2019-11-19
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Publication No.: US11217487B2Publication Date: 2022-01-04
- Inventor: Yi-Chen Lo , Li-Te Lin , Pinyen Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L21/3213 ; H01L21/02 ; H01L21/28

Abstract:
A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.
Public/Granted literature
- US20200176323A1 SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE Public/Granted day:2020-06-04
Information query
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