Invention Grant
- Patent Title: Chip package assembly with enhanced interconnects and method for fabricating the same
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Application No.: US16044363Application Date: 2018-07-24
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Publication No.: US11217550B2Publication Date: 2022-01-04
- Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/3065 ; H01L21/78

Abstract:
An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.
Public/Granted literature
- US20200035635A1 CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME Public/Granted day:2020-01-30
Information query
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