An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low-voltage junction formed in the substrate, and a second low-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first low-voltage junction and the second low-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low-voltage junction formed in the substrate, and a fourth low-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction.