Invention Grant
- Patent Title: Ion beam etching fabricated sub 30nm Vias to reduce conductive material re-deposition for sub 60nm MRAM devices
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Application No.: US16894033Application Date: 2020-06-05
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Publication No.: US11217746B2Publication Date: 2022-01-04
- Inventor: Yi Yang , Dongna Shen , Zhongjian Teng , Jesmin Haq , Yu-Jen Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L43/12
- IPC: H01L43/12 ; H01L43/08 ; G11C11/16 ; H01L43/02 ; B82Y25/00

Abstract:
A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
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