Invention Grant
- Patent Title: Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM
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Application No.: US16875827Application Date: 2020-05-15
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Publication No.: US11218165B2Publication Date: 2022-01-04
- Inventor: Jian Chen , Ying Zhang
- Applicant: Alibaba Group Holding Limited
- Applicant Address: KY George Town
- Assignee: Alibaba Group Holding Limited
- Current Assignee: Alibaba Group Holding Limited
- Current Assignee Address: KY George Town
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Shun Yao
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/09 ; G11C29/52 ; G11C29/42 ; G06F11/10

Abstract:
One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device. The data block and the second-dimension ECC bits are mapped to separate physical addresses in the storage device.
Public/Granted literature
- US20210359704A1 MEMORY-MAPPED TWO-DIMENSIONAL ERROR CORRECTION CODE FOR MULTI-BIT ERROR TOLERANCE IN DRAM Public/Granted day:2021-11-18
Information query
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