Invention Grant
- Patent Title: Hardware based packet replication at tail end node
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Application No.: US16842422Application Date: 2020-04-07
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Publication No.: US11218336B2Publication Date: 2022-01-04
- Inventor: Swami Narayanan , Ambrish Mehta , Venkatesh Srinivasan , Raghava Sivaramu , Ayan Banerjee
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Polsinelli PC
- Main IPC: H04L12/46
- IPC: H04L12/46 ; H04L12/04 ; H04L29/06

Abstract:
Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.
Public/Granted literature
- US20200235959A1 HARDWARE BASED PACKET REPLICATION AT TAIL END NODE Public/Granted day:2020-07-23
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