Invention Grant
- Patent Title: Forward error correction mechanism for data transmission across multi-lane links
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Application No.: US16991681Application Date: 2020-08-12
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Publication No.: US11223446B2Publication Date: 2022-01-11
- Inventor: Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H04L1/00
- IPC: H04L1/00

Abstract:
Systems and devices can include a first port of a first device coupled to a second port of a second device across a multi-lane link. The first port can augment a data block with error correcting code by distributing error correcting code evenly across each lane of the data block, wherein each lane of the data block includes a same number of error correcting code. The first port can transmit the data block with the per-lane error correcting code to the second port across the multi-lane link. The second port can determine error correcting code based on the error correcting code bits received in the data block, and perform error correction on the symbols of the data block based on the error correcting code received.
Public/Granted literature
- US20200374037A1 FORWARD ERROR CORRECTION MECHANISM FOR DATA TRANSMISSION ACROSS MULTI-LANE LINKS Public/Granted day:2020-11-26
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